Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!cs.utexas.edu!milano!bigtex!james
From: james@bigtex.uucp (James Van Artsdalen)
Newsgroups: comp.sys.ibm.pc
Subject: Re: NS16550 ACE question
Message-ID: <8045@bigtex.uucp>
Date: 15 Sep 88 21:15:13 GMT
References: <1357@sun.soe>
Reply-To: james@bigtex.UUCP (James Van Artsdalen)
Organization: F.B.N. Software, Austin TX
Lines: 21

In article <1357@sun.soe>, nelson@clutx.clarkson.edu wrote:

> According to the documentation, the NS16550 ACE (essentially an 8250 with
> a FIFO) asserts THRE *only* when the transmit queue is empty.  [...]
> And it WILL work but only if THRE is asserted as long as there is room in
> the FIFO.

You're not considering another important purpose of the 16550A (don't
use the 16550!): to lessen the system load.  If the 16550A gave an
interrupt each time there was a free spot in the queue, you would get
an interrupt for each character sent.  Instead of this, it generates
an interrupt each time the queue is nearly empty, meaning every 16
interrupts.  Much less overhead.

I can't find my documentation at the moment, but I believe that the
THRE is asserted when the queue becomes empty, with the implication
that the shift register is still processing the last byte.  This means
there is a full character time before the output channel becomes idle.
-- 
James R. Van Artsdalen    ...!uunet!utastro!bigtex!james     "Live Free or Die"
Home: 512-346-2444 Work: 328-0282; 110 Wild Basin Rd. Ste #230, Austin TX 78746