Path: utzoo!attcan!uunet!mcvax!ukc!eagle.ukc.ac.uk!icdoc!qmc-cs!harlqn!andrew From: andrew@jung.harlqn.uucp (Andrew Watson) Newsgroups: comp.arch Subject: Re: How the Japanese will win the MIPS wars with SPARC Summary: You'll need extra support to use SPARC w/o register windows Message-ID: Date: 28 Sep 88 17:04:17 GMT References: <58@zeno.MN.ORG> <91@zeno.MN.ORG> Sender: news@harlqn.UUCP Organization: Harlequin Limited, Cambridge, UK Lines: 46 In-reply-to: gene@zeno.MN.ORG's message of 16 Sep 88 05:33:06 GMT In article <91@zeno.MN.ORG> gene@zeno.MN.ORG (Gene H. Olson) writes: [words about how SPARC, as a 'public domain' architecture, will sweep the board, just as unix, as semi-public domain software, has] * There was a heated discussion for awhile about register windows. No one pointed out that the SPARC architecture accesses register windows only with explicit instructions, that the architecture spec requires only two of them (one for user mode, one for software traps), and that they need not be otherwise used. SPARC offers you the option of register windows. If they don't help in some situations (they seem to work well in others) there is no reason you need use them. Since only two of them are required, there is no serious penalty if they are unused by an implementation. Its clearly a win-win situation. Just a small point from a compiler-writer who's been attempting to write a code generator for the SPARC that *does* ignore register windows - it's possible, but the architecture really doesn't support it. To explain - the whole point of windows is to minimise overall memory traffic by eliminating most stack read/writes. If the on-chip register file does overflow, then stack traffic is necessary, but the whole file can be dumped in one go, potentially using an efficient memory burst mode (on the 4/110, for instance). If you don't use windows, you have to emulate a stack yourself - not particularly difficult or slow, but it will cost you two instructions and a memory reference per push/pop, and three instructions for a call. A RISC without windows designed to use memory burst modes to boost performance is the Acorn ARM. It has a pair of instructions to push/pop an arbirary selection of its 16 (or is it 32?) registers in a single register-per-memory-cycle burst. Used in conjunction with a callee-saves calling convention, this allows one burst-mode access to the stack per call to save the return address, static link and all the registers that the callee wishes to use. -- Regards, Andrew. +-----------------------------------------------------------------------------+ | Andrew Watson, Harlequin Limited, andrew@uk.co.harlqn | | Barrington Hall, Barrington, Tel: +44 223 872522 | | Cambridge CB2 5RG, UK Fax: +44 223 872519 | +-----------------------------------------------------------------------------+