Path: utzoo!utgpu!water!watmath!clyde!mcdchg!motmpl!ron
From: ron@motmpl.UUCP (Ron Widell)
Newsgroups: comp.arch
Subject: Re: PEP (really domain architectures)
Message-ID: <975@motmpl.UUCP>
Date: 5 Oct 88 15:46:31 GMT
References: <936@raspail.UUCP> <3265@geaclib.UUCP>
Reply-To: ron@motmpl.UUCP (Ron Widell)
Organization: Motorola Semiconductor, Minneapolis, MN
Lines: 29

In article <3265@geaclib.UUCP> daveb@geaclib.UUCP (David Collier-Brown) writes:
=In article <2550@sultra.UUCP>, dtynan@sultra.UUCP (Der Tynan) writes:
=| Rather than have a standard U/S bit in the CPU status register, it might make
=| more sense to assign it to each I-page in a paged-MMU system....
=
=From article <936@raspail.UUCP>, by bga@raspail.UUCP (Bruce Albrecht):
=instead of purely nested rings, and may be found in several forms on
=machines ranging from mainframes (Honeywell-Bull, naturely) to

That was the reason for the CALLM and RTM instructions on the 68020
and the access level protection mechanism on the 68851 (at the request
of a single customer who, subsequently, never used them).

=protection you usually set up another stack, dump all registers,
=flush the fpp, etc... Probably not a good idea for a Unix-like
=machine, where people are already complaining about the overhead
=involved in system calls.

This is probably why they were never used (other than having to rewrite
an existing OS and all of the applicatios SW :-)). Just a single
instruction, but lots of bus cycles :-(.

=--dave (spread thinly) c-b

-- 
Ron Widell				|UUCP: motmpl!ron
Motorola Semiconductor Products, Inc.,	|Voice:(612)941-6800
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