Path: utzoo!attcan!uunet!seismo!sundc!pitstop!sun!decwrl!labrea!rutgers!uwvax!oddjob!tank!uxc!uxc.cso.uiuc.edu!a.cs.uiuc.edu!m.cs.uiuc.edu!grunwald
From: grunwald@m.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: RISC speed madness
Message-ID: <3300033@m.cs.uiuc.edu>
Date: 4 Oct 88 04:38:00 GMT
References: <985@srs.UUCP>
Lines: 7
Nf-ID: #R:srs.UUCP:985:m.cs.uiuc.edu:3300033:000:237
Nf-From: m.cs.uiuc.edu!grunwald    Oct  3 23:38:00 1988


You don't need much 40ns RAM. You can have a multi-level cache
stagging to cheaper RAM, i.e. 32Kb of 40ns cache for 1Mb of 80ns cache
for 32Mb of 200ns ram.

Recent papers (last sigarch?) show that this is a very reasonable thing
to do.