Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: Some 1987 patents of interest
Message-ID: <1988Oct13.165717.10262@utzoo.uucp>
Organization: U of Toronto Zoology
References: <5511@hoptoad.uucp> <16406@shemp.CS.UCLA.EDU> <352@laic.UUCP> < <9865@cup.portal.com> <2567@sultra.UUCP>
Date: Thu, 13 Oct 88 16:57:17 GMT

In article <2567@sultra.UUCP> dtynan@sultra.UUCP (Der Tynan) writes:
>With all this talk of a Sun RAS/CAS pseudo-patent, my curiosity is piqued.
>Would someone care to give a description of the patent? ...

The basic notion is, since the RAMs want the address in two parts, one at
a time, if you choose things like page size carefully, you can hand the
RAMs the untranslated low-order bits first, and run the high-order bits
through the MMU while the RAMs are contemplating the low-order bits.  The
result is that the MMU imposes no time penalty, because you have to wait
until the RAMs are ready for the second half of the address anyway.  Of
course, with modern RAMs this does mean that your MMU has to be pretty
damned fast.  It also, unfortunately, means that your pages have to be
pretty large, since half the chip-level address has to go through without
translation.  (For example, with 1Mb RAMs you need 10 untranslated bits,
and if you address to the byte and have 32-bit memory, two more bits go
for byte number, so you need 12 bits of address within a page and your
minimum page size is 4KB.  This gets worse if you want to plan for 4Mb
RAMs or for a faster-but-compatible machine with 64-bit-wide memory.)
If you've ever wondered why the pages on the Suns are so big, now you
know...
-- 
The meek can have the Earth;    |    Henry Spencer at U of Toronto Zoology
the rest of us have other plans.|uunet!attcan!utzoo!henry henry@zoo.toronto.edu