Path: utzoo!attcan!uunet!ncrlnk!ncr-sd!hp-sdd!ucsdhub!ucsd!rutgers!tut.cis.ohio-state.edu!bloom-beacon!bu-cs!encore!pinocchio!corbin
From: corbin@pinocchio.Encore.COM (Steve Corbin)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Speeding up old PC's
Summary: 400ns seems fine to me
Message-ID: <3850@encore.UUCP>
Date: 11 Oct 88 01:18:45 GMT
References: <3009@dalcs.UUCP> <16800379@clio>
Sender: news@encore.UUCP
Reply-To: corbin@pinocchio.UUCP (Steve Corbin)
Organization: Encore Computer Corp, Marlboro, MA
Lines: 32

In article <16800379@clio> berger@clio.las.uiuc.edu writes:
>
>No - but I think that person is mistaken.  I'd like to see how he
>calculates that 400 ns rams should be sufficiently fast.
>
>			Mike Berger
>			Department of Statistics 
>			University of Illinois 

I just took a quick look at the data books and here's what I got:

	It takes 4 clocks ticks for a bus cycle on the 8086/8088.
	The maximum address valid time is 110ns and the data setup
	to the trailing edge of T3 is 30ns.

	Without going into the PC schematics you can assume that there
	is probably an address buffer and a data buffer in the path.
	Assuming a 74LS373 for buffering/latching this adds another 54ns
	(2 * 27ns).

	At 4.77mhz each clock tick is 209.6ns for a total of 629ns
	to perform a read.  629-110-30-54 = 435ns.

Depending upon how adversely the design of the control path affects the
access time, it is entirely possible that 400ns rams will work.

Disclaimer:  The real answer can be found by a detailed timing analysis
of the actual design which is far from what I did.


Stephen Corbin	    UUCP:	{bu-cs,decvax,necntc,talcott}!encore!corbin
		    Internet:	corbin@multimax.ARPA