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From: buck@siswat.UUCP (A. Lester Buck)
Newsgroups: comp.unix.xenix,comp.unix.questions,comp.unix.microport,comp.sys.ibm.pc
Subject: Re: *nix performance
Summary: information about DMA on the PC and AT
Message-ID: <330@siswat.UUCP>
Date: 11 Oct 88 05:11:51 GMT
References: <9902@ico.ISC.COM> <736@starfish.Convergent.COM> <1901@van-bc.UUCP> <1488@ssc.UUCP>
Distribution: na
Organization: Photon Graphics, Houston
Lines: 64

In article <1488@ssc.UUCP>, fyl@ssc.UUCP (Phil Hughes) writes:
> In article <4032@tekgvs.GVS.TEK.COM>, keithe@tekgvs.GVS.TEK.COM (Keith Ericson) writes:
> > In article <2733@ima.ima.isc.com> johnl@ima.UUCP (John R. Levine) writes:
> 
> > >On machines with a PC AT bus DMA is rarely a win. It takes so long to get and
> > >release the bus that it's faster to...
> 
> > We use Micom-Interlan NI5010 network interface boards around here.
> > Their instructions indicate NOT to use DMA on an AT-class machine
> > because a tight loop doing the data transfers is faster than the
> > AT's DMA...
> 
> Anyway, is DMA just slower when I have an idle CPU to do the transfer or
> is there something magic that makes the CPU useless while DMA is running?

The PC BIOS uses DMA to do disk I/O because the DMA chip can do it
faster than the minimum loop of 8088 instructions.

The AT BIOS uses INS/OUTS instructions because they are (slightly) faster
than the equivalent DMA transfers.  As the 80186/88 hardware reference
states "The INS and OUTS instructions move a string of bytes or words
at bus bandwidth speed between memory and an I/O port.  This is
essentially a DMA transfer in one in-line instruction."
Of course, the AT BIOS has nothing better to be doing during the
transfer.

As far as the DMA subsystem capabilities, they are described in
the Intel data sheet for the 8237A (Microprocessor and Peripheral
Handbook, Vol. 1) and a few minor implementation details in the
AT Technical Reference.  From the data sheet, there are four
modes of DMA service: (1) single transfer, (2) block transfer,
(3) demand transfer, and (4) cascade mode.  On the AT,
channel 4 on the second 8237A cascades from the first chip.
In single transfer mode, the DMA chip transfers one byte, then
gives up the bus and must be restarted.  "In 8080A, 8085H, 8088,
or 8086 systems, this will ensure one full machine cycle
execution between DMA transfers."  The block mode and demand mode
differ only in that block mode needs the DREQ request line only
active at the beginning, while demand mode will save its state
and give up the bus when DREQ goes off, then pick up where it
left off when it is reasserted.  Both of these modes continue
transfering until an internal programmed count is exhausted.
For the demand mode, "Thus transfers may continue until the I/O
device has exhausted its data capacity.  After the I/O device
has had a chance to catch up, the DMA service is re-established
by means of a DREQ."

There are several ways to implement the DMA hardware on the I/O
device, and I don't have a broad experience in this area.  One
interesting card I own is an Emulex IB02 SCSI Host Adapter
for the PC (8-bit) bus.  (This card is not very popular and
a bit old and expensive, but it uses a good SCSI interface chip and is
very flexible with switches for DMA channels, DMA modes, IRQ line,
etc.)  The possible selections for DMA modes are: single byte,
4-byte demand, and 8-byte demand.  Hardware on the card gives
up the bus after that many bytes in the demand modes.  Of course,
the driver has to program the 8237A for the matching mode.
Recommended is single-byte for all PC's, 8-byte demand for AT's
running DOS, and 4-byte demand for AT multitasking OS's.  This allows
more CPU processing during DMA transfers and keeps interrupt latency
lower.

-- 
A. Lester Buck		...!uunet!nuchat!moray!siswat!buck