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From: thomas@uplog.se (Thomas Hameenaho)
Newsgroups: comp.sys.mac,comp.sys.mac.programmer
Subject: Re: Bus and Address Error insights (was Re: Listing of error...)
Keywords: bus error address error macII interrupts
Message-ID: <305@uplog.se>
Date: 3 Oct 88 12:55:53 GMT
References: <975@psu-cs.UUCP> <630@ethz.UUCP>
Reply-To: thomas@uplog.UUCP (Thomas Hameenaho)
Organization: TeleLOGIC Uppsala AB
Lines: 26


In article <630@ethz.UUCP> macman@ethz.UUCP (Danny Schwendener) writes:

>The MMU will generate a Bus Error request if you access an invalid 
>memory address. When you have an Address Error caused by a dangling 
>handle, it might happen that you access an invalid memory adress. The
>MMU then generates a Bus Error.

example deleted

>Or when it tries to WRITE on an odd address boundary. (reading
>is allowed, writing not. Another mysterious feature of the 68020).
>

Crap!

The 68020 can both read AND write words and long-words on odd addresses.
What it can't do is to fetch instructions from odd byte addresses.

The 68020 also checks the address BEFORE it is put out on the pins so
it should be impossible to get both address and bus error for the same cycle.
-- 
Real life:	Thomas Hameenaho		Email:	thomas@uplog.{se,uucp}
Snail mail:	TeleLOGIC Uppsala AB		Phone:	+46 18 189406
		Box 1218			Fax:	+46 18 132039
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