Path: utzoo!attcan!uunet!l5comp!scotty From: scotty@l5comp.UUCP (Scott Turner) Newsgroups: comp.unix.microport Subject: Re: Bell Tech W.G.E. use with "sissy" unix Summary: Read my lips :) Message-ID: <445@l5comp.UUCP> Date: 9 Oct 88 09:37:54 GMT References: <438@l5comp.UUCP> <428@eecea.eece.ksu.edu> <554@micropen> Reply-To: scotty@l5comp.UUCP (Scott Turner) Organization: L5 Computing, Edmonds, WA Lines: 32 In article <554@micropen> dave@micropen (David F. Carlson) writes: >In article <428@eecea.eece.ksu.edu>, terry@eecea.eece.ksu (Terry Hull) writes: >> In article <438@l5comp.UUCP> scotty@l5comp.UUCP (Scott Turner) writes: >> >easily. But if your system has a SRAM cache you may be in for a VERY ^^^ Please note! >> >nasty surprise! > >I have used machines with several caching schemes (Intel chips and Everex >proprietary) and they always cache only memory they known about: main mother >board memory. If a device has a memory map in the AT bus structure *it* must Well I'm glad at least a few companies are on the ball. It did cross my mind that it would have been smarter for Mylex to only cache ram that the BIOS POST found during startup, but alas the cacheable memory size in the Mylex design is cast into a PAL. If Mylex designed their cache in this fashion so can others. And then again others can get it right. Hence the phrase "may be in" in my warning. Rather than something more concrete like "We're all screwed, run for the hills!" ;) I will also note that Bell gave me no such warning about caches. I am trying to save others from a nasty surprise. >No caching is done of these areas or no polling IO would ever succeed. >(I'm pretty sure it does. :-) DOS is no different from UNIX in this regard.) Are you confirming that the Everex boards, and those based on the Intel cache controller, do work with the WGE right out of the box? (Your posting was a little hard for me to understand.) Scott Turner scotty@l5comp -or- uunet!l5comp!scotty