Path: utzoo!attcan!uunet!tektronix!orca!tekecs!frip!andrew
From: andrew@frip.gwd.tek.com (Andrew Klossner)
Newsgroups: comp.unix.wizards
Subject: Re: Data in text segment
Message-ID: <10440@tekecs.TEK.COM>
Date: 7 Oct 88 19:27:21 GMT
References: <159@taux02.UUCP> <7124@rpp386.Dallas.TX.US> <10420@tekecs.TEK.COM> <7599@rpp386.Dallas.TX.US>
Sender: andrew@tekecs.TEK.COM
Organization: Tektronix, Wilsonville, Oregon
Lines: 25

[]

		"The point missed by the second poster is that
		"separate I&D space" is usually taken to mean two
		separate but overlapping address spaces."

	"Incorrect.  This poster did take that fact into account.  The
	more reasonable CPU's have status lines from the CPU which
	indicate the nature of the instruction.  For example, the
	MC68000 supports separate I&D space at the hardware level ..."

The original point was that somebody thought to put unmodified data
into a shared text segment, and it was noted that this wouldn't work on
a machine like the PDP-11/45 using a magic number 411 object file,
"separate I&D".

Yes the hardware has a line to tell the memory whether I or D is being
requested.  But the program has no control over that line!  There's no
general use "load from instruction space" instruction on any
architecture I've looked at, so there's no way for a program to use
data in a separated instruction space.  (Sometimes there's a "load from
user's instruction space," but it's restricted to supervisor mode.)

  -=- Andrew Klossner   (uunet!tektronix!tekecs!frip!andrew)    [UUCP]
                        (andrew%frip.gwd.tek.com@relay.cs.net)  [ARPA]