Xref: utzoo comp.arch:6623 alt.next:142
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From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch,alt.next
Subject: Re: The NeXT Problem
Message-ID: <5986@winchester.mips.COM>
Date: 16 Oct 88 23:44:34 GMT
References: <26435@ucbvax.BERKELEY.EDU> <5498@juniper.uucp> <1988Oct16.022032.29382@utzoo.uucp> <5549@juniper.uucp>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 30

In article <5549@juniper.uucp> chari@juniper.UUCP (Christopher Michael Whatley) writes:
>In article <1988Oct16.022032.29382@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:
>>In article <5498@juniper.uucp> chari@juniper.UUCP (Christopher Michael Whatley) writes:
>>>[Cisc comatible risc (ok it did sound dumb)]
>>
>>Sigh.  Isn't it sad:  even in comp.arch, people have forgotten what "RISC"
>>means.  That's like trying to build a Concorde that's compatible with a
>>donkey cart.
>
>Excuse me for not being precise enough. To quote.... "It's a sort of RISC/CISC
>hybrid [which is] pin-compatible with the 68030. [It] supports the motorola
>instruction set at between 1 and 2 instructions per cycle..."

1) The 68030 is "RISCier" than the 68020.  Specifically, it went from
3 cycle bus access to 2 cycle access, and cycle counts were pared down
elsewhere, I believe.  Note that, as we've said before, you can always
make CISC go faster by heavier pipelining+parallelism, but usually
at a cost in hardware complexity and gate-count.  The NeXT box does use
a 68030.

2) "between 1 and 2 instructions per cycle": I think this is backwards.
I might believe 3-4 cycles/instruction.  Lots of people are talking about
dual-issue micros, which is what you need to get 1-2 instrs/cycle, but
I can't think of any that are yet on the market, and making CISCs do that
will be truly exciting.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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