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From: usenet@cps3xx.UUCP (Usenet file owner)
Newsgroups: comp.arch,alt.next
Subject: Re: RISC v. CISC
Summary: CISC = RISC + support
Message-ID: <890@cps3xx.UUCP>
Date: 17 Oct 88 17:49:41 GMT
References: <156@gloom.UUCP>
Reply-To: rang@cpswh.cps.msu.edu (Anton Rang)
Organization: Michigan State University, Computer Science Dept.
Lines: 47
In-reply-to: cory@gloom.UUCP's message of 17 Oct 88 14:54:02 GMT

In article <156@gloom.uucp>, Cory Kempf (decvax!encore!gloom!cory) writes:
>First, there is no good reason that all of the cache and pipeline
>enhancements cannot be put on to a CISC processor.

  This is definitely true.  Look at the caching on the 68030, or the
Z80,000 for instance.  The advantage a RISC gives you is more space
for caching logic, though--so you can have a bigger cache (or more
registers, or possibly both).

>Second, to perform a complex task, a RISC chip will need more
>instructions than a CISC chip.

  Right!  Unless you add special hardware to help it with the most
common complex tasks, in which case you're heading right back to CISC.
Nick Tredennick gives an interesting characterization of RISC in his
paper from the IEEE CompCon '86 panel on RISC vs. CISC:

	Cut a MC68000 in half across the middle just below the control
	store.  Throw away the part with the instruction decoders,
	control store, state machine, clock phase generators, branch
	control, interrupt handler, and bus controller.  What you will
	have left is a RISC "microprocessor."  All the instructions
	execute in one cycle.  The design is greatly simplified.  The
	chip is smaller.  And the apparent performance is vastly
	improved. [stuff omitted] ...try to build a system using this
	wonderful new chip.  You have to rebuild on the card the parts
	you just cut off.  Good luck trying to service the microcode
	interface at the 'microprocessor' clock rate.

  I think this is a great characterization of a particular segment of
the debate: that which talks about chip complexity.  Now, instruction
set complexity is a bit different, and I'm not convinced one way or
the other on that yet (though I lean toward CISC).  The recent
discussion of "the 68030 is RISCier than the 68020" and "a RISC
compatible with the 68020" doesn't have anything to do with the
instruction set--just the chip design.  Maybe there's a better term
for it than RISC....
  Just my thoughts...

		Anton

Disclaimer: I'm into software, not hardware!

+----------------------------------+------------------------+
| Anton Rang (grad student)	   | "UNIX: Just Say No!"   |
| Michigan State University	   | rang@cpswh.cps.msu.edu |
+----------------------------------+------------------------+