Xref: utzoo comp.arch:6650 alt.next:165
Path: utzoo!hoptoad!pacbell!ames!mailrus!tut.cis.ohio-state.edu!rutgers!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch,alt.next
Subject: Re: RISC v. CISC --more misconceptions
Message-ID: <18931@apple.Apple.COM>
Date: 17 Oct 88 19:40:49 GMT
References: <156@gloom.UUCP>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 45

[]
>In article <156@gloom.UUCP> cory@gloom.UUCP (Cory Kempf) writes:
>A while back, I was really hot on the idea of RISC.  Then a friend 
>pointed out a few things that set me straight...
>
>First, there is no good reason that all of the cache and pipeline
>enhancements cannot be put on to a CISC processor.

  Some are trying to do it, but they can't do it as well as a RISC processor
  because they don't have room on the chip, because they're busy supporting
  instructions and addressing modes that hardly ever get used.

>Second, to perform a complex task, a RISC chip will need more
>instructions than a CISC chip.

  First of all, not necessarily true. Second of all, so what?  The number
  of instructions used by RISCS has been greatly exaggerated. First generation
  RISCS may have a code expansion of 50% in bytes. However, this is a static
  measurement. It doesn't mean that the inner loops will use twice as many
  cycles. And, since the datapath of a RISC machine is simpler, its cycles
  are likely faster.

>Third, given the same level of technology for each (ie caches, pipelines,
>etc), a microcode fetch is faster than a memory fetch.

  Perhaps, but the microcode is only good for one thing: interpreting macro-
  code. A the code in a cache is good for whatever I happen to be executing
  at the time.

>As an aside, the 68030 can do a 32 bit multiply in about (If I remember 
>correctly -- I don't have the book in front of me) 40 cycles.  A while
>back, I tried to write a 32 bit multiply macro that would take less 
>than the 40 or so that the '030 took.  I didn't even come close (even 
>assuming lots of registers and a 32 bit word size (which the 6502 
>doesn't have)).  

Check out the ASPLOS II proceedings. There is an article the by Dan Magenheimer
of HP explaining how the do 11 cycle average multiplies, without a multiplier,
and without a multiply step instruction. Besides, if you have a RISC machine,
and multiply is truly important, the you have room for multiply support, up
to having a full multiplier. You may find, howver, that it won't make any
difference in your performance because no one needs an integer multiplier very
often. Like a lot of things that RISC designers have left out.

--
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