Xref: utzoo comp.arch:6822 alt.next:244 Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!bellcore!texbell!sugar!ficc!peter From: peter@ficc.uu.net (Peter da Silva) Newsgroups: comp.arch,alt.next Subject: Re: RISC v. CISC (really comments on many postings: LONG) Message-ID: <2005@ficc.uu.net> Date: 25 Oct 88 20:49:23 GMT References: <156@gloom.UUCP> <6865@winchester.mips.COM> Organization: SCADA Lines: 23 In article <6865@winchester.mips.COM>, mash@mips.COM (John Mashey) writes: > [7] This is very confusing. Most RISCs use 3-address operations, i.e., > reg3 = reg1 OP reg2. > rather than just 2-address ops: > reg1 = reg1 OP reg2 > Certainly, these include, but are not limited to: IBM 801, HP PA, > MIPS R2000, SPARC, 29K, 88K. I've been out of things for a while, but didn't RISCs use to use either stack or load-store architecture? Or was that just RISC-1? Anyway, I brought up two CISCy features I'd read about here recently. That was one. Addressing modes are the other. And addressing modes... even just indexing and autoincrement... are pretty CISCy. Just pointing out that RISC isn't a religion... it's a technique. -- Peter da Silva `-_-' Ferranti International Controls Corporation "Have you hugged U your wolf today?" uunet.uu.net!ficc!peter Disclaimer: My typos are my own damn business. peter@ficc.uu.net