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From: cory@gloom.UUCP (Cory Kempf)
Newsgroups: comp.arch,alt.next
Subject: RISC v. CISC (was The NeXT problem)
Summary: RISC v. CISC
Message-ID: <156@gloom.UUCP>
Date: 17 Oct 88 14:54:02 GMT
Sender: news@husc6.harvard.edu
Organization: Alloy Computer Products, Framingham, Mass.
Lines: 25

A while back, I was really hot on the idea of RISC.  Then a friend 
pointed out a few things that set me straight...

First, there is no good reason that all of the cache and pipeline
enhancements cannot be put on to a CISC processor.

Second, to perform a complex task, a RISC chip will need more
instructions than a CISC chip.

Third, given the same level of technology for each (ie caches, pipelines,
etc), a microcode fetch is faster than a memory fetch.

As an aside, the 68030 can do a 32 bit multiply in about (If I remember 
correctly -- I don't have the book in front of me) 40 cycles.  A while
back, I tried to write a 32 bit multiply macro that would take less 
than the 40 or so that the '030 took.  I didn't even come close (even 
assuming lots of registers and a 32 bit word size (which the 6502 
doesn't have)).  



-- 
Cory Kempf
UUCP: {decvax, bu-cs}!encore!gloom!cory
revised reality... available at a dealer near you.