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From: gillies@p.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: ETA-10: CMOS or ECL?
Message-ID: <76700054@p.cs.uiuc.edu>
Date: 16 Oct 88 01:35:00 GMT
References: <3539@phri.UUCP>
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Nf-From: p.cs.uiuc.edu!gillies    Oct 15 20:35:00 1988


There are some people who predict that most supercomputers of the
future will be made of CMOS.

CMOS gates use power mainly when they switch logic levels.  The power
consumption curve is a bell curve, with a peak halfway between the logic
levels.  Very few other types of logic (ECL, TTL) have this property, i.e.
that in steady state, the power consumption is almost NIL.

To increase CMOS speed, you just shrink the design rules of the CMOS
circuit (less than 1 micron?) and pay attention to transmission line
effects, etc.  You want this in a supercomputer, so that data
transmission time is minimized, maximizing CPU speed.

Try this in any other technology (esp. ECL), and your supercomputer
will probably melt down, because so much power is being dissipated
constantly, in a very small area (like 1 cubic foot).  It's a physics
/ thermodynamics homework problem to prove that a sufficiently small
ECL computer with enough gates cannot be cooled with known cooling
technologies.


P.S. I stopped taking VLSI courses 4 years ago, so please excuse my
ignorance if some of this is inaccurate.


Don Gillies, Dept. of Computer Science, University of Illinois
1304 W. Springfield, Urbana, Ill 61801      
ARPA: gillies@cs.uiuc.edu   UUCP: {uunet,ihnp4,harvard}!uiucdcs!gillies