Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!ucla-cs!loving
From: loving@lanai.cs.ucla.edu
Newsgroups: comp.arch
Subject: Transmission line (was CMOS or ECL)
Message-ID: <16939@shemp.CS.UCLA.EDU>
Date: 18 Oct 88 19:59:16 GMT
Sender: news@CS.UCLA.EDU
Reply-To: loving@CS.UCLA.EDU ()
Organization: UCLA Computer Science Department
Lines: 18

I don't care who wrote it, but this was posted:

>Transmission line effects on a chip? Just how big *are* your chips
>anyway? 

The only reason that transmission line effects are not serious is because
RC delays dominate.  The speed of light is 29.979 cm/nsec; RC delays down
busses on chips (1u lines, 1mm long, .01 ohm/sq, .03fF/sq u) are on the order
of 0.3 to 1.0 nano seconds.  This does not take into account the time to
charge the gate capacitance of the transistor(s) at the other end of this
1000u long line.  Now if we used transmission lines instead of 'RC delay
lines' the time to drive the signal down the line would be somewhere on
the order of c/2 (speed of light) or more like 1 pico second.  1 nano
second is pretty killer on a 10 or 15 nsec chip.  1 picosecond would not
be.

Mike Loving
loving@lanai.cs.ucla.edu