Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!bloom-beacon!apple!amdcad!weitek!jetsun!krish
From: krish@jetsun.WEITEK.COM (Krishnan Sridhar)
Newsgroups: comp.arch
Subject: Re: The NeXT Problem
Message-ID: <737@jetsun.WEITEK.COM>
Date: 18 Oct 88 20:39:12 GMT
References: <26435@ucbvax.BERKELEY.EDU> <5498@juniper.uucp> <5941@winchester.mips.COM>
Organization: WEITEK Corporation, Sunnyvale CA
Lines: 24


In article <5941@winchester.mips.COM>, mash@mips.COM (John Mashey) writes:
> In article <5498@juniper.uucp> chari@juniper.UUCP (Christopher Michael Whatley) writes:
> ...
> >They are supposedly developing their own RISC chip that is compatible with the
> >030. I don't know any more than that. I read this in a rumour column. 

> 
> This defies all logic.
> a) If it's compatible with an 030, it's not a RISC.  If it's a design
> that makes the 68K architecture go faster (quite possible), it's still
> CISC, but maybe it's called a 68040.  Do you think that NeXT thinks they
> can do that better than Moto?


  Not quite true.  A RISC version of 68K can be made and with
  appropriate compiler, can be made fully compatibile with their ancestors.
  Frankly, RISC is not such a "narrow" concept as you make it appear. The 
  concepts of RISC are fairly general and can be adapted to newer designs,
  still maintaining compatibility. Note, the compiler has to be a lot smarter,
  but given the fact that RISC itself requires a smart compiler to fully
  realize it's potentials, I don't think it's that big a deal.

- krish