Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!apple!amdcad!weitek!jetsun!krish
From: krish@jetsun.WEITEK.COM (Krishnan Sridhar)
Newsgroups: comp.arch
Subject: Re: ETA-10: CMOS or ECL?
Message-ID: <738@jetsun.WEITEK.COM>
Date: 18 Oct 88 21:43:19 GMT
References: <3539@phri.UUCP> <76700054@p.cs.uiuc.edu> <23287@amdcad.AMD.COM>
Organization: WEITEK Corporation, Sunnyvale CA
Lines: 14

In article <23287@amdcad.AMD.COM>, phil@diablo.amd.com (Phil Ngai) writes:
> In article <76700054@p.cs.uiuc.edu> gillies@p.cs.uiuc.edu writes:

> Transmission line effects on a chip? Just how big *are* your chips
> anyway? 
> 

 Size of the chip is not the only determining factor here. A few years ago, I
 worked on a piece of logic (for a supercomputer) using Fairchild's (may it's
 soul rest in peace) 100K ECL gate arrays. The characterization curves for
 the gate array cells assumed transmission line effects inside the chip ...
 The gate array could support about 3000 gates.

 - Krish