Path: utzoo!utgpu!attcan!uunet!vsi!friedl
From: friedl@vsi.COM (Stephen J. Friedl)
Newsgroups: comp.arch
Subject: Re: ETA-10: CMOS or ECL?
Summary: CMOS
Message-ID: <887@vsi.COM>
Date: 17 Oct 88 04:46:50 GMT
References: <3539@phri.UUCP> <76700054@p.cs.uiuc.edu>
Organization: V-Systems, Inc. -- Santa Ana, CA
Lines: 28

In article <76700054@p.cs.uiuc.edu>, gillies@p.cs.uiuc.edu writes:
> 
> There are some people who predict that most supercomputers of the
> future will be made of CMOS.
> 
> CMOS gates use power mainly when they switch logic levels.  The power
> consumption curve is a bell curve, with a peak halfway between the logic
> levels.  Very few other types of logic (ECL, TTL) have this property, i.e.
> that in steady state, the power consumption is almost NIL.

This also means that as speeds go up, the low-power benefits of
CMOS drop pretty dramatically.  CMOS in a standby state can run
off two strips of metal in a potato, but when you clock it very
fast the current rises quickly.  There are some parts of a system
that will be used only occasionally, but [stretching memory here[
a CPU made of CMOS can take nearly as much power as NMOS.

> P.S. I stopped taking VLSI courses 4 years ago, so please excuse my
> ignorance if some of this is inaccurate.

P.S. - I've never had any VLSI courses, so please excuse my
ignorance if some of this is inaccurate

     Steve
-- 
Steve Friedl    V-Systems, Inc.  +1 714 545 6442    3B2-kind-of-guy
friedl@vsi.com     {backbones}!vsi.com!friedl    attmail!vsi!friedl
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