Path: utzoo!attcan!uunet!husc6!mailrus!ncar!noao!arizona!naucse!sbw From: sbw@naucse.UUCP (Steve Wampler) Newsgroups: comp.arch Subject: CISCy RISC? RISCy CISC? Message-ID: <973@naucse.UUCP> Date: 17 Oct 88 02:47:48 GMT Organization: Northern Arizona University, Flagstaff, AZ Lines: 34 (I just know I'm going to regret this, but hey, it's late.) Just what is it about RISC vs. CISC that really sets them apart? With my very naive understanding, it really seems that the big difference is that RISC models will let one get into the high speed technologies faster (which we really haven't seen out on the market place yet). Other than that, I doubt I would care whether my machine is RISC or CISC, if I can even tell them apart. A case in point. I know of a not-yet-announced machine (perhaps never to be announced machine) that has just about the largest instruction set I can imagine (not to mention the 15+ addressing modes). However, the machine has many of the features that gives some RISC chips their performance - zillions of registers, big I and D caches, etc., and gets most instructions down to 1 cycle per instruction (some of the more complex instructions 'appear' to run faster because they work on multiple bytes at a time). The result is a 12.5MHz machine that runs 25000 (claimed) dhrystones using what I would call a 'throwaway' C compiler. The manufacturers 'know' they can push the clock up to 30MHz, which (my estimate, this time) would give >40000 dhrystones. (Hey, I'm into software, I don't know what's true in hardware.) Now, I've missed most of the RISC/CISC wars, but these seem to me to be very fine numbers, at least compared with the uVAXen I've played with (all of which cost more). How do they compare to current RISCs? I'd bet pretty much the same. I personally couldn't care which machine I'd own (not that I can afford any). When the really fast chips come in, I bet the RISC machines are the first to come out, but still, is there something that will keep CISC from catching up? -- Steve Wampler {....!arizona!naucse!sbw}