Path: utzoo!attcan!uunet!husc6!mailrus!ames!pasteur!ucbvax!amdcad!diablo!phil
From: phil@diablo.amd.com (Phil Ngai)
Newsgroups: comp.arch
Subject: Re: ETA-10: CMOS or ECL?
Message-ID: <23287@amdcad.AMD.COM>
Date: 17 Oct 88 20:02:38 GMT
References: <3539@phri.UUCP> <76700054@p.cs.uiuc.edu>
Sender: news@amdcad.AMD.COM
Reply-To: phil@diablo.AMD.COM (Phil Ngai)
Organization: Advanced Micro Devices, Inc. Sunnyvale CA
Lines: 12

In article <76700054@p.cs.uiuc.edu> gillies@p.cs.uiuc.edu writes:
|To increase CMOS speed, you just shrink the design rules of the CMOS
|circuit (less than 1 micron?) and pay attention to transmission line
|effects, etc.  

Transmission line effects on a chip? Just how big *are* your chips
anyway? 

"In the West, to waste water is not to consume it, to let it flow unimpeded 
and undiverted down rivers. Use of water is, by definition, beneficial use."
(from _Cadillac Desert_)
Phil Ngai, {ucbvax,decwrl,allegra}!amdcad!phil or phil@amd.com