Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!rochester!uhura.cc.rochester.edu!sunybcs!boulder!ncar!tank!uxc!uxc.cso.uiuc.edu!a.cs.uiuc.edu!m.cs.uiuc.edu!grunwald
From: grunwald@m.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: ETA-10: CMOS or ECL?
Message-ID: <3300035@m.cs.uiuc.edu>
Date: 18 Oct 88 02:09:00 GMT
References: <3539@phri.UUCP>
Lines: 7
Nf-ID: #R:phri.UUCP:3539:m.cs.uiuc.edu:3300035:000:306
Nf-From: m.cs.uiuc.edu!grunwald    Oct 17 21:09:00 1988


Again, the caveat of old knowledge, but..

The switching speed of CMOS is limited by charge disappation time. By reducing
the voltage difference between zero and one states, you can increase the
switching speed. This also takes less current, because you're pushing less
electrons around to charge an area.