Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!bloom-beacon!bu-cs!purdue!decwrl!sun!ember!dre
From: dre%ember@Sun.COM (David Emberson)
Newsgroups: comp.arch
Subject: Re: ETA-10: CMOS or ECL?
Summary: Not a RISC v.s. CISC comment, anyway...
Message-ID: <73616@sun.uucp>
Date: 19 Oct 88 17:57:03 GMT
References: <3539@phri.UUCP> <76700054@p.cs.uiuc.edu> <23287@amdcad.AMD.COM>
Sender: news@sun.uucp
Lines: 9

In article <23287@amdcad.AMD.COM>, phil@diablo.amd.com (Phil Ngai) writes:
> 
> Transmission line effects on a chip? Just how big *are* your chips
> anyway? 

Well, if you clock the chip at ~100 GHz I suppose you would have to worry
about it! :-)

				Dave