Xref: utzoo comp.arch:6718 alt.next:206
Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!uccba!uceng!rsexton
From: rsexton@uceng.UC.EDU (robert sexton)
Newsgroups: comp.arch,alt.next
Subject: Re: The NeXT Problem
Summary: Re: RISC is Cheaper
Message-ID: <330@uceng.UC.EDU>
Date: 19 Oct 88 15:08:48 GMT
References: <521@fabscal.UUCP> <5024@cbmvax.UUCP> <23298@amdcad.AMD.COM>
Organization: Univ. of Cincinnati, College of Engg.
Lines: 11

While RISC may be cheaper(smaller design, less silicon) what you are really
doing is shifting the cost burden onto the rest of the system.  The high
memory bandwidth of the RISC design means more high speed memory, bigger
high-speed caches.  With a CISC design, you put all of the high speed silicon
on one chip, lowering the cost of all the support circuitry and memory.

-- 
Robert Sexton, University of Cincinnati
rsexton@uceng.uc.edu tut.cis.ohio-state.edu!uccba!uceng!rsexton
Box Full O' Transputers... The Breakfast with MIPS
I do not speak for UC, They don't speak for me.