Path: utzoo!attcan!uunet!ncrlnk!ncrcae!hubcap!gatech!rutgers!att!alberta!calgary!dataspan!deraadt From: deraadt@dataspan.UUCP (Theo De Raadt) Newsgroups: comp.arch Subject: Re: The NeXT Problem Message-ID: <250@dataspan.UUCP> Date: 16 Oct 88 20:41:19 GMT References: <26435@ucbvax.BERKELEY.EDU> <5498@juniper.uucp> Organization: DataSpan Inc., Calgary AB Canada Lines: 25 In article <5498@juniper.uucp>, chari@juniper.uucp writes: >In article <26435@ucbvax.BERKELEY.EDU> pchris@ucbarpa.Berkeley.EDU writes: >>It seems that the NeXT machine may have a few problems: >> >>1) Outdated Processor Technology: NeXT just missed the wave of fast RISC >> processors. The 5 MIPS 68030 is completely out performed by the currently >> available RISC chips (Motorola, MIPS, Sparc) that run at approximately... > >They are supposedly developing their own RISC chip that is compatible with the >030. I don't know any more than that. I read this in a rumour column. >(Grain-o-salt) Doesn't 20 RISC MIPS equal about 5 CISC MIPS? I am getting sick and tired of this RISC/CISC battle. Come on guys, measure RISC instructions against CISC microcode level instructions and they work out to about the same thing. As far as I can see, it appears that we are always battling memory speeds. Not trying to start a flame war, but 030's are faster than Sun 4's. I puke trying to write assembly on RISC machines. I love CISC though, because you find your bottleneck, and just jump in and start ripping some things out, and rewrite the routine..-- _____ _ ----------------------------------- / / / / \ _ _ /_/_ Theo de Raadt: (403) 289-4620 / /_ _ ___ __/_ /__/ _\ _\ __/ / DATASPAN / / /