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From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: RISC v. CISC
Message-ID: <10194@cup.portal.com>
Date: 19 Oct 88 19:34:20 GMT
References: <156@gloom.UUCP> <890@cps3xx.UUCP>
Organization: The Portal System (TM)
Lines: 44

>>Second, to perform a complex task, a RISC chip will need more
>>instructions than a CISC chip.

For most purposes the difference is not important, maybe 20% more with
the top at 40%.  But the working set is the important issue where caches
are concerned.  Is the RISC's cache working set bigger than the CISC's?
Maybe, I don't know for sure.  I wrote a fairly big program, 40K lines
(an incrementally-compiling simulator for the 68000, fun!) last year.
The code size was 15% bigger on the 29K than on the Vax. Admittedly, the
29K compiler is much better than the vax's.  But does anyone ever ask
*why* it is much better?

Slightly paraphrased Nick Tredennick:
>	Cut a MC68000 in half; Throw away the instruction decoders,
>	control store, state machine, clock phase generators, branch
>	control, interrupt handler, and bus controller.  What you will
>	have left is a RISC "microprocessor."  All the instructions

Not true.  RISCs do not throw away the bus controller, the interrupt
handler, the insruction decoder, branch control, etc. etc.  He is just
griping because it is so small on the chip that it looks like it has
been thrown out.  :-) :-)
>	execute in one cycle.  The design is greatly simplified.  The
>	chip is smaller.  And the apparent performance is vastly
>	improved. [stuff omitted] ...try to build a system using this
>	wonderful new chip.  You have to rebuild on the card the parts
>	you just cut off.  Good luck trying to service the microcode
>	interface at the 'microprocessor' clock rate.
There are existence proofs:  several systems are doing it.  What more 
could he want?

>The recent discussion of "the 68030 is RISCier than the 68020" and "a RISC
>compatible with the 68020" doesn't have anything to do with the
>instruction set--just the chip design.  Maybe there's a better term
>for it than RISC....

The 68030 core is *exactly the same* (maybe a Moto guy can comment?) as
the 68020's core.  They shrunk it and added the data cache.  The bus
controller now supports 4-word bursts.  The cache line size changed.

What has been left out of this discussion is the software side of the
issue.  The almighty Compiler can save us from our sins!  It is our
saviour!  Long live common subexpression elimination!  Hail to the code
reorganizer!  Praise the register allocator!  Jim Bakker, watch out!