Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ames!think!bloom-beacon!mit-eddie!rutgers!bellcore!tness7!texbell!sugar!ficc!peter
From: peter@ficc.uu.net (Peter da Silva)
Newsgroups: comp.arch
Subject: RISC/CISC and the wheel of life.
Message-ID: <1945@ficc.uu.net>
Date: 19 Oct 88 15:45:28 GMT
References: <26435@ucbvax.BERKELEY.EDU> <5498@juniper.uucp> <6496@spool.cs.wisc.edu>
Organization: SCADA
Lines: 18

I have noticed one very interesting thing about RISCs lately... they are
getting quite sophisticated instruction sets. 3-address operations and
addressing modes aren't what I used to associate with RIS, but if you look
at them they turn out to be refinements of older RISCs.

What's happening, of course, is that the chips are so much faster than any
sort of affordable RAM that it's worthwhile to put more into the instructions.
The speed of the system as a whole goes up, since the chip can still handle
all three register references in one external clock. No point in fetching
instructions any faster than that...

I don't know whether this will end up with a one-instruction-per-cycle 68000,
before memory/cache technology catches up, but it's always interesting to
watch the wheel turn.
-- 
Peter da Silva  `-_-'  Ferranti International Controls Corporation.
"Have you hugged  U  your wolf today?"            peter@ficc.uu.net
Disclaimer: I accept full responsibility for my own actions...
	    but NOT until I've had my first cup of coffee.