Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!mailrus!purdue!decwrl!hplabs!nsc!stevew
From: stevew@nsc.nsc.com (Steve Wilson)
Newsgroups: comp.arch
Subject: Re: Transmission line (was CMOS or ECL)
Message-ID: <7147@nsc.nsc.com>
Date: 19 Oct 88 19:35:10 GMT
References: <16939@shemp.CS.UCLA.EDU>
Reply-To: stevew@nsc.nsc.com.UUCP (Steve Wilson)
Organization: National Semiconductor, Sunnyvale
Lines: 31

In article <16939@shemp.CS.UCLA.EDU> loving@CS.UCLA.EDU () writes:
>I don't care who wrote it, but this was posted:
>
>>Transmission line effects on a chip? Just how big *are* your chips
>>anyway? 
>
>The only reason that transmission line effects are not serious is because
>RC delays dominate.  The speed of light is 29.979 cm/nsec; RC delays down
>busses on chips (1u lines, 1mm long, .01 ohm/sq, .03fF/sq u) are on the order
>of 0.3 to 1.0 nano seconds.  This does not take into account the time to
>charge the gate capacitance of the transistor(s) at the other end of this
>1000u long line.  Now if we used transmission lines instead of 'RC delay
>lines' the time to drive the signal down the line would be somewhere on
>the order of c/2 (speed of light) or more like 1 pico second.  1 nano
>second is pretty killer on a 10 or 15 nsec chip.  1 picosecond would not
>be.

I've done lotsa work with ECL, and a bit with ECL gate-arrays.  If I
recall correctly, you have to pull signals internal to a ECL gate-array
down with a terminating resistor just like you have to externally.  I
didn't do any of the timing analysis for the gate-arrays on the project
I was on, but I do seem to recall that the major timing problems was 
capacitive loading.  Some of the faster gate-array families had better
drive capabilities for a given length of metal.  This seemed to dominate
the real performance of the array.  In summary, are you guys sure your
not confusing the requirment for a pull down resistor for having to 
deal with transmission lines?

Steve Wilson
National Semiconductor

[The above is my opinion, not those of my employer.]