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From: jsp@b.gp.cs.cmu.edu (John Pieper)
Newsgroups: comp.arch
Subject: single-cycle 680X0
Message-ID: <3350@pt.cs.cmu.edu>
Date: 19 Oct 88 22:20:17 GMT
Sender: netnews@pt.cs.cmu.edu
Reply-To: jsp@b.gp.cs.cmu.edu (John Pieper)
Organization: Carnegie-Mellon University, CS/RI
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Actually, I heard a guy from Motorola talking about their n+1st generation
680X0 machine -- they run an internal clock at 2X the external clock, and
play some other tricks to get 14 MIPS effective, 25 MIPS max @ 25 MHz. Seems
to me that CISC designers could do this very effectively to get ahead of the
RISC types (modulo the design time).

BTW, as far as design time goes, you have to take the RISC argument with a
grain of salt. the 68030 is only a little different that the 68020, but with
technology advances and just a few man-years they more than tripled the
speed of the initial 68020 release (in 82?). The 68040 will take the same
basic ALU design, and add the FPU. This shouldn't require too much redesign.
The point is that a good CISC design can be modified (added to) as quickly
as a major redesign of a RISC chip. What really counts is who can sell their
instruction set.
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John Pieper				 jsp@n.sp.cs.cmu.edu
Computer Science Department
Carnegie-Mellon University
Pittsburgh, Pa 15213
	"Supersonicous Siliconous"? What we need is Warp speed!