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From: kds@blabla.intel.com (Ken Shoemaker)
Newsgroups: comp.arch,alt.next
Subject: Re: The NeXT Problem
Message-ID: <3069@mipos3.intel.com>
Date: 21 Oct 88 18:03:28 GMT
References: <26435@ucbvax.BERKELEY.EDU>
Sender: news@mipos3.intel.com
Reply-To: kds@blabla.UUCP (Ken Shoemaker)
Organization: Santa Clara Microprocessor Division, Intel Corp., Santa Clara, CA
Lines: 12

Of course, another obvious reason for not using any of the currently
available RISCs (except for maybe the 29000) is system implementation costs.
If you don't put a cache on a MIPS, the system won't run like a jackrabbit.
With the SPARC you need to implement your own MMU.  And the component
costs of 88000s and Clippers with their custom MMU/cache chips are almost 
half the cost of the whole machine!  And then we can start to talk about
availability of production volumes of reasonably debugged parts...
--------
If you break a law to prove a law, you're on pretty shakey moral grounds 
						-- Ian Shoales
Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California
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