Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!cwjcc!hal!nic.MR.NET!tank!ncar!noao!asuvax!nud!xroads!edge!doug From: doug@edge.UUCP (Doug Pardee) Newsgroups: comp.arch Subject: Re: CISCy RISC? RISCy CISC? Summary: Edge, new CISC machines, and RISC mainframes Message-ID: <1293@edge.UUCP> Date: 21 Oct 88 16:59:38 GMT References: <973@naucse.UUCP> <10192@cup.portal.com> Organization: Edge Computer Corporation, Scottsdale, AZ Lines: 67 An all-in-one posting from a not-exactly-unbiased source... >For an example of an architecture that's 68000 compatible and RISCy to >the point of executing most instructions in a single clock cycle, look >no farther than the Edge computer. However, if you want this on a >single chip, instead of a bunch of gate arrays, you'll have to wait. Just so's everyone will know... we had a clash with Leading Edge computers over the name, and our lawyers advised that since until recently all of our units went to OEMs who put their own names on them, the "Edge" name isn't well known enough to be worth fighting for. So last month, with Leading Edge's blessing, we became Edgcore Technology, Inc. No, I don't like the name Edgcore. But then, I thought that "Apple" was a really stupid name for a computer and that "IBM Personal Computer" was an awfully unoriginal name. :-) ----- Next subject and author.... >Even so, there are no new CISC designs >being done, that I know of. I presume that this means "instruction set designs", not computer designs. There have been a ton of new systems using old instruction sets recently; for example Amdahl just came out with a stupendous box using the 370 set. As for designing new instruction sets, the fact that CISC has attained a level of stability while new RISC instruction sets seem to appear each month is hardly a point in favor of RISC. New instruction sets usually appear because there are perceived major flaws in the existing sets. Edge chose to implement the 680x0 instruction set in our box because we considered it to be a very practical and powerful set and we didn't think we could do much better with an Edge-designed set. We *did* add a few instructions that we thought were missing, though... Intel, on the other hand, found it worthwhile to design a new instruction set for the 80386. I can't imagine why :-) ----- Next subject and author.... >The problem is that many of the current generation of risc machines do >not support interlocked instructions. > ... >... if I want to build mainframes based on multiple high >performance risc chips, I find myself up the creek. The incorrect assumption here is that you would want to build a mainframe using RISC technology -- that RISC technology has anything to offer at that price/cost level. As we at Edgcore have shown, it is both possible and practical to implement CISC instruction sets at speeds faster than RISC. But -- it doesn't all fit on one chip. Yet. In a mainframe design, who cares if it fits on one chip? Jeez, in our E2000 system we need an entire triple-high VME card jam-packed with surface-mount parts just to hold the *caches* that we need to have to keep from starving the CPU. The complexity and board area of the CPU itself is insignificant compared to that required by mainframe-sized multi-level memory systems. Nobody's going to be building a "single board mainframe" with today's DRAM and SRAM technologies. If/when those RAM technologies do reach that point, it's likely that our 1-instruction-per-clock-cycle 680x0 will fit on one chip too. Of course, by then there'll be a different definition of "mainframe"... -- Doug Pardee, Edgcore Technology (formerly Edge Computer), Scottsdale, AZ {ames,hplabs,sun,amdahl,allegra}!oliveb!edge!doug uunet!ism780c!edge!doug