Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!cornell!uw-beaver!uw-june!pardo
From: pardo@june.cs.washington.edu (David Keppel)
Newsgroups: comp.arch
Subject: Re: LISPMs not RISC? - Re: CISCy RISC? RISCy CISC?
Message-ID: <6177@june.cs.washington.edu>
Date: 22 Oct 88 03:06:00 GMT
References: <973@naucse.UUCP> <10192@cup.portal.com> <19191@apple.Apple.COM> <16921@ames.arc.nasa.gov>
Reply-To: pardo@cs.washington.edu (David Keppel)
Organization: U of Washington, Computer Science, Seattle
Lines: 25

raymond@pioneer.arc.nasa.gov.UUCP (Eric A. Raymond) writes:
>malcolm@Apple.COM (Malcolm Slaney) writes:
>>[ somebody? ]
>>>must be backward compatible.  Even so, there are no new CISC designs
>>>being done, that I know of.  

Oh, heck, there's some (relatively) new supercomputer being produced
by some subsidiary of CDC (I think?) that was written up in "digital
review" a month or so ago.  It is described as "VCISC" -- Very CISC.
It includes as part of its basic instructin set a whole smear of
vector opcodes, which can operate on chunks of memory up to 1 page;
several page sizes are supported, I believe that the largest is 64K
64-bit words = 1/2 Mbyte.  Physical memories of up to about 2Gbytes or
2Gwords (I forget) are availabale, liquid Nitrogen is optional.
Next model is due in December or so and should bench the Livermore
Loops with the best of the Crays.

Also, while CISC is out of vogue in new industry designs at the
moment, there are plenty of Universities building microcoded
processors (read "CISC"?).

	;-D on  ( Just don't page fault very often.... )  Pardo
-- 
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