Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ames!amdahl!pyramid!prls!mips!rogerk
From: rogerk@mips.COM (Roger B.A. Klorese)
Newsgroups: comp.arch
Subject: Re: The NeXT Problem
Message-ID: <6243@wright.mips.COM>
Date: 20 Oct 88 02:25:38 GMT
References: <26435@ucbvax.BERKELEY.EDU> <5498@juniper.uucp> <250@dataspan.UUCP>
Reply-To: rogerk@wright.UUCP (Roger B.A. Klorese)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 21

In article <250@dataspan.UUCP> deraadt@dataspan.UUCP (Theo De Raadt) writes:
>I am getting sick and tired of this RISC/CISC battle. Come on guys, measure
>RISC instructions against CISC microcode level instructions and they work out
>to about the same thing. As far as I can see, it appears that we are always
>battling memory speeds. Not trying to start a flame war, but 030's are
>faster than Sun 4's.

Yes, but Sun 4's are not representative of leading-edge RISC design, or of
efficient RISC architecture.
 
>I puke trying to write assembly on RISC machines. 

Funny, while I don't recommend doing it (as our compilers can usually do
at least as good a job as you can), I can show you testimonials to the ease
of writing MIPS assembler.

Remember, SPARC ~= RISC.
-- 
Roger B.A. Klorese                               MIPS Computer Systems, Inc.
{ames,decwrl,prls,pyramid}!mips!rogerk	                  928 E. Arques Ave.
rogerk@mips.COM (rogerk%mips.COM@ames.arc.nasa.gov)     Sunnyvale, CA  94086
I don't think we're in toto anymore, Kansas.                 +1 408 991-7802