Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!uflorida!haven!mimsy!chris
From: chris@mimsy.UUCP (Chris Torek)
Newsgroups: comp.arch
Subject: Re: RISC v. CISC (was The NeXT problem
Message-ID: <14112@mimsy.UUCP>
Date: 22 Oct 88 15:44:51 GMT
References: <10193@cup.portal.com> <5863@killer.DALLAS.TX.US>
Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742
Lines: 17

In article <5863@killer.DALLAS.TX.US> elg@killer.DALLAS.TX.US (Eric Green)
writes:
>For example, the high-end Vaxen have a pipelined MICROARCHITECTURE. It
>is almost impossible to effectively pipeline the macroarchitecture of
>a Vax, because of the multitude of instruction set formats (almost as
>bad as the 680x0). 

While the 680x0 have a number of formats (and thus lengths), one of the
nice properties of its instruction set is that the first word tells you
the length of the entire instruction.  This is not true of the Vax
instruction set: on the Vax, the first byte is simply the opcode, and you
must read all of the operand bytes to discover the location of the next
instruction.  In other words, you must (almost) fully decode the current
instruction before you can begin decoding the next.
-- 
In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163)
Domain:	chris@mimsy.umd.edu	Path:	uunet!mimsy!chris