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From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: LISPMs not RISC? - Re: CISCy RISC? RISCy CISC?
Message-ID: <10359@cup.portal.com>
Date: 22 Oct 88 20:04:25 GMT
References: <973@naucse.UUCP> <10192@cup.portal.com> <19191@apple.Apple.COM
Organization: The Portal System (TM)
Lines: 14

>Anyway, nobody ever said that RISC meant lots of registers.

Maybe nobody ever said it, but I would be willing to go out on limb
and say it if someone asked. :-)

>Please flame on me and set me straight if I'm wrong.

Do we now need a group "alt.masochists"?  :-)

>Not that the d-machines were nkown for speed ....

They had plenty of speed (Dorado had (I think) an ECL implementation,
a 45 ns cycle time, and sophistiated caching long before it came down
to that class of machine in the real world).  They just hid the speed
below a few layers of microcode. :-)