Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!cbmvax!golux!eric From: eric@golux.UUCP (Eric S. Raymond) Newsgroups: comp.arch Subject: Big register files, the dominating RISC win? Message-ID: Date: 22 Oct 88 11:47:06 GMT References: <1468@wayback.uucp> <1618@garth.uucp> Organization: Justified Ancients of Muammu Lines: 28 In article <1618@garth.uucp>, walter@garth.UUCP (Walter Bays) writes: > I think there's > no point in becoming dogmatic about register/cache/memory/stack/window > organizations. The goal is speed, which can be achieved in many > different ways. Well...there may be a *little* point to being dogmatic about large windowed register files. I recall a fascinating paper from '85 or so by some guys that investigated (by simulation) various ways of RISCifying a 68000. Turned out that of all the `RISC'-like features, the windowed register file gave the best bang-for-buck in terms of throughput increase on a typical compiled-code instruction mix (this makes sense, as well-written compiled code is generally real heavy on procedure-call and argument-passing overhead). In fact, the speed gain from the register file was so big that it rendered the wins from other added simulation features (pipelining, decrease in microcode overhead, and a bunch of other things I don't recall, tried in various combinations) insignificant by comparison. It seems these mostly cancelled themselves out by increasing the demand on processor-to-memory bandwidth. Over the years since, I've found the results of that paper excellently predictive as to what designs would *really* cook once they hit the real world... -- Eric S. Raymond (the mad mastermind of TMN-Netnews) UUCP: ...!{uunet,att,rutgers}!snark!eric = eric@snark.UUCP Post: 22 S. Warren Avenue, Malvern, PA 19355 Phone: (215)-296-5718