Path: utzoo!utgpu!attcan!uunet!husc6!mit-eddie!killer!elg From: elg@killer.DALLAS.TX.US (Eric Green) Newsgroups: comp.arch Subject: Re: RISC v. CISC (was The NeXT problem Message-ID: <5863@killer.DALLAS.TX.US> Date: 21 Oct 88 05:07:02 GMT References: <10193@cup.portal.com> Organization: The Unix(R) Connection, Dallas, Texas Lines: 33 >>A while back, I was really hot on the idea of RISC. Then a friend >>pointed out a few things that set me straight... >>First, there is no good reason that all of the cache and pipeline >>enhancements cannot be put on to a CISC processor. > > True for the simple instructions in the CISC instruction set. Not so > true for the ones with complex addressing modes, etc. Fixed instruction > size, format, and prevention of page-boundary crossings are very good > things to do. This limits the CISCy ness of an instruction set, or the For example, the high-end Vaxen have a pipelined MICROARCHITECTURE. It is almost impossible to effectively pipeline the macroarchitecture of a Vax, because of the multitude of instruction set formats (almost as bad as the 680x0). What this seems to mean is that the difference between CISC and RISC lies more in instruction format than in number of instructions (as someone else on this list pointed out). I suspect that you could have a "CISC" just as fast as a "RISC" IF the instruction format is fairly regular (i.e., no "expanding opcode" hyper-compressed formats need apply). True, a compact opcode takes less memory space. BUT, it has to UNcompacted before it's used... Someone else on this newsgroup mentioned that Seymour Cray's secret to a fast computer was to put as few gates as possible in critical paths. Anybody got a reference for where Cray said that? In any event, on too many CISCS, instruction decode is that critical path... -- Eric Lee Green ..!{ames,decwrl,mit-eddie,osu-cis}!killer!elg Snail Mail P.O. Box 92191 Lafayette, LA 70509 It's understandable that Mike Dukakis thinks he can walk on water. He's used to walking on Boston harbor.