Path: utzoo!utgpu!attcan!uunet!portal!cup.portal.com!
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: single-cycle 680X0
Message-ID: <10250@cup.portal.com>
Date: 20 Oct 88 19:46:18 GMT
References: <3350@pt.cs.cmu.edu>
Organization: The Portal System (TM)
Lines: 22

>680X0 machine -- they run an internal clock at 2X the external clock, and
>play some other tricks to get 14 MIPS effective, 25 MIPS max @ 25 MHz. Seems
>to me that CISC designers could do this very effectively to get ahead of the
>RISC types (modulo the design time).

Sigh.  Can RISC do this too?  Yes.  This is an implementation technique, not
an inherent advantage.

>The 68040 will take the same
>basic ALU design, and add the FPU. This shouldn't require too much redesign.
>The point is that a good CISC design can be modified (added to) as quickly
>as a major redesign of a RISC chip. What really counts is who can sell their
>instruction set.

The basic ALU design might be preserved, by they are getting the performance
they claim by implementing the subset of the 68000 instruction set that are
simple with RISC techniques.  This does little or nothing for the complex
instructions and addressing modes, so they re-write the compilers to use only
or mostly the simple instructions.  Is this CISC?  This is certainly not
something that "...shouldn't require too much redesign"!

I think the 68040 will be neat.  But I wonldn't want to design or pay for it.