Path: utzoo!utgpu!attcan!uunet!cbmvax!snark!eric From: eric@snark.UUCP (Eric S. Raymond) Newsgroups: comp.arch Subject: Re: RISC/CISC and the wheel of life. Message-ID: Date: 21 Oct 88 14:50:47 GMT References: <26435@ucbvax.berkeley.edu> <5498@juniper.uucp> Organization: Golden Apple Gotterdammerung Promotions, Inc. Lines: 22 In article <1945@ficc.uu.net>, peter@ficc.uu.net (Peter da Silva) writes: > I have noticed one very interesting thing about RISCs lately... they are > getting quite sophisticated instruction sets. 3-address operations and > addressing modes aren't what I used to associate with RIS, but if you look > at them they turn out to be refinements of older RISCs. My understanding of RISC philosophy suggests that 3-address ops and fancy addressing modes are only regarded as *symptoms* of the RISC problem -- poor match of instructions to compiler code generator capabilities, excessive miceocode-interpretation overhead in both cycles and chip real estate. If your compiler can make effective use of three-address instructions, and you've got CAD tools smart enough to gen logic for them onto an acceptably small % of the chip area (so that you don't have to give up on more important features like a big windowed register file and on-chip MMU), then I don't see any problem with calling the result a RISC. But, then, I am only-an-egg when it comes to hardware... -- Eric S. Raymond (the mad mastermind of TMN-Netnews) UUCP: ...!{uunet,att,rutgers}!snark!eric = eric@snark.UUCP Post: 22 S. Warren Avenue, Malvern, PA 19355 Phone: (215)-296-5718