Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!cwjcc!mailrus!ames!amdahl!mat From: mat@amdahl.uts.amdahl.com (Mike Taylor) Newsgroups: comp.arch Subject: Re: RISC v. CISC (was The NeXT problem) Message-ID: Date: 25 Oct 88 21:34:54 GMT References: <156@gloom.UUCP> <310@lynx.zyx.SE> <332@pvab.UUCP> <15964@agate.BERKELEY.EDU> Organization: Amdahl Corporation, Sunnyvale CA Lines: 24 In article <15964@agate.BERKELEY.EDU>, matloff@bizet.Berkeley.EDU (Norman Matloff) writes: > ^^^^^^^^ > > Based on parameters of Berkelely RISC I or II, the register-saving > might take on the order of 0.1 msec. If the quantum size is set to > be in the range claimed to be typical in the Peterson and Silberschatz > OS book, i.e. 10 to 100 msec, then we see that the register-saving > issue for a RISC with lots of regiters has probably been greatly > overemphasized. > > Comments? > > Norm Matloff I have trouble with milliseconds, but it depends on the workload and the OS variant. How about transaction processing, where there may be as few as (say) 4K cycles between process switches in a message-oriented environment. (I know this has nothing to do with NeXT). Then cache and register effects may be very significant - particularly if you dump a large register file into a cache. -- Mike Taylor ...!{hplabs,amdcad,sun}!amdahl!mat [ This may not reflect my opinion, let alone anyone else's. ]