Path: utzoo!yunexus!geac!syntron!jtsv16!uunet!mcvax!enea!pvab!robert
From: robert@pvab.UUCP (Robert Claeson)
Newsgroups: comp.arch
Subject: Re: RISC v. CISC (was The NeXT problem)
Message-ID: <332@pvab.UUCP>
Date: 22 Oct 88 16:59:54 GMT
Article-I.D.: pvab.332
References: <156@gloom.UUCP> <310@lynx.zyx.SE>
Organization: ERBE Data AB, Sweden
Lines: 16

In article <310@lynx.zyx.SE>, grzm@zyx.SE (Gunnar Blomberg) writes:

> It seems to me that a typical
> well-designed RISC chip should actually need *fewer* instructions
> (statically and dynamically) to perform most tasks than your typical CISC
> chip, for the following reasons:
> 
>    * The RISC chip has more registers.

The more registers, the more to save at every context switch in a typical
OS (such as UNIX). Which will slow things down if you have many processes
running.
-- 
Robert Claeson, ERBE DATA AB, P.O. Box 77, S-175 22 Jarfalla, Sweden
Tel: +46 758-202 50   Fax: +46 758-197 20
Email: robert@pvab.se (soon rclaeson@erbe.se)