Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: RISC v. CISC (was The NeXT problem)
Message-ID: <1988Oct26.232336.15680@utzoo.uucp>
Organization: U of Toronto Zoology
References: <156@gloom.UUCP> <310@lynx.zyx.SE> <332@pvab.UUCP>
Date: Wed, 26 Oct 88 23:23:36 GMT

In article <332@pvab.UUCP> robert@pvab.UUCP (Robert Claeson) writes:
>The more registers, the more to save at every context switch in a typical
>OS (such as UNIX). Which will slow things down if you have many processes
>running.

This one comes up regularly, sigh...  Whether it gives you a net slowdown
or not depends on how much context-switching is going on, how long a
process runs between context switches (i.e. how much chance it has to
take advantage of having that data in registers), and how much you care
about interrupt latency.  If context switches are not *too* common and
latency is not a big deal, lots of registers can be a huge net win even
if it does slow context switching.  The same comment applies to non-
writethrough caches.
-- 
The dream *IS* alive...         |    Henry Spencer at U of Toronto Zoology
but not at NASA.                |uunet!attcan!utzoo!henry henry@zoo.toronto.edu