Path: utzoo!yunexus!geac!syntron!jtsv16!uunet!seismo!sundc!pitstop!sun!decwrl!ucbvax!agate!bizet.Berkeley.EDU!matloff
From: matloff@bizet.Berkeley.EDU (Norman Matloff)
Newsgroups: comp.arch
Subject: Re: RISC v. CISC (was The NeXT problem)
Message-ID: <15964@agate.BERKELEY.EDU>
Date: 25 Oct 88 03:53:32 GMT
Article-I.D.: agate.15964
References: <156@gloom.UUCP> <310@lynx.zyx.SE> <332@pvab.UUCP>
Sender: usenet@agate.BERKELEY.EDU
Reply-To: matloff@iris.ucdavis.edu (Norm Matloff)
Organization: EECS, UC Davis
Lines: 27

In article <332@pvab.UUCP> robert@pvab.UUCP (Robert Claeson) writes:
>In article <310@lynx.zyx.SE>, grzm@zyx.SE (Gunnar Blomberg) writes:

*> It seems to me that a typical
*> well-designed RISC chip should actually need *fewer* instructions
*> (statically and dynamically) to perform most tasks than your typical CISC
*> chip, for the following reasons:
*> 
*>    * The RISC chip has more registers.
*
*The more registers, the more to save at every context switch in a typical
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
*OS (such as UNIX). Which will slow things down if you have many processes,
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
*running.
^^^^^^^^

Based on parameters of Berkelely RISC I or II, the register-saving
might take on the order of 0.1 msec.  If the quantum size is set to
be in the range claimed to be typical in the Peterson and Silberschatz
OS book, i.e. 10 to 100 msec, then we see that the register-saving
issue for a RISC with lots of regiters has probably been greatly
overemphasized.

Comments?

   Norm Matloff