Path: utzoo!yunexus!geac!syntron!jtsv16!uunet!seismo!sundc!pitstop!sun!amdcad!ames!ncar!tank!uxc!uxc.cso.uiuc.edu!urbsdc!aglew
From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: ETA-10: CMOS or ECL?
Message-ID: <28200216@urbsdc>
Date: 20 Oct 88 14:58:00 GMT
Article-I.D.: urbsdc.28200216
References: <3539@phri.UUCP>
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Nf-ID: #R:phri.UUCP:3539:urbsdc:28200216:000:932
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Oct 20 09:58:00 1988


..> CMOS power consumption.

Dynamic power consumption dominates in CMOS, especially
as frequency goes up. As I understand it, there are two
components of dynamic power consumption: (1) the inherent
power consumption as you go through charge/discharge cycles
on your nodes; (2) the transient that occurs if both the
n and p networks are switched on at the same, brief, time, in 
transition.

The first seems to be inherent.

Cannot the second be controlled by making it impossible to have
both sides on at the same time. Eg. instead of using PHI and PHIBAR
to control top and bottom halves of a dynamic circuit, not use
PHI_P = 011000 and PHI_N = 000011, ie. use non-overlapping clocks
in the same clock module, instead of in different cascaded stages.
NB. this is *not* the same as two or four phase clocking with
overlapping clocks, at least in the textbooks I've seen.

This is probably a very novice question, but I'm trying...