Path: utzoo!yunexus!geac!syntron!jtsv16!uunet!seismo!sundc!pitstop!sun!amdcad!crackle!tim
From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: RISC v. CISC (was The NeXT problem)
Message-ID: <23367@amdcad.AMD.COM>
Date: 25 Oct 88 17:10:19 GMT
Article-I.D.: amdcad.23367
References: <156@gloom.UUCP> <310@lynx.zyx.SE> <332@pvab.UUCP> <15964@agate.BERKELEY.EDU>
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Reply-To: tim@crackle.amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc. Sunnyvale CA
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In article <15964@agate.BERKELEY.EDU> matloff@iris.ucdavis.edu (Norm Matloff) writes:
| Based on parameters of Berkelely RISC I or II, the register-saving
| might take on the order of 0.1 msec.  If the quantum size is set to
| be in the range claimed to be typical in the Peterson and Silberschatz
| OS book, i.e. 10 to 100 msec, then we see that the register-saving
| issue for a RISC with lots of regiters has probably been greatly
| overemphasized.
| 
| Comments?

Actually, the register saving is more likely to be on the order of 10 to
20 microseconds (order of magnitude less than the 0.1 you suggest). 
Comparing 100 context-switches per second to 350,000 procedure calls per
second, it isn't hard to see where to concentrate your optimization
efforts...


	-- Tim Olson
	Advanced Micro Devices
	(tim@crackle.amd.com)