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From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch,comp.sys.next
Subject: Re: RISC v. CISC (really comments on many postings: LONG)
Message-ID: <7009@winchester.mips.COM>
Date: 26 Oct 88 07:17:54 GMT
Article-I.D.: winchest.7009
References: <156@gloom.UUCP> <6865@winchester.mips.COM> <2005@ficc.uu.net>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 23

In article <2005@ficc.uu.net> peter@ficc.uu.net (Peter da Silva) writes:
>In article <6865@winchester.mips.COM>, mash@mips.COM (John Mashey) writes:
>> [7]  This is very confusing.  Most RISCs use 3-address operations, i.e.,
>> 	reg3 = reg1 OP reg2.
>> 			rather than just 2-address ops:
>> 	reg1 = reg1 OP reg2

>I've been out of things for a while, but didn't RISCs use to use either
>stack or load-store architecture? Or was that just RISC-1?
RISCs are mostly load/store designs, but maybe I misread what you
meant.  Most RISCs use load/store designs, where a single load/store
accesses 1 memory object, which generally can't cross page (or
even naturally-aligned object) boundaries.  Some of them allowed
for simple indexed and/or auto-increment/decrement addressing.

I don't know of any RISCs that have instructions that touch 3 addresses
in memory, so I assume you were asking about the 3-operand forms
(in registers), which are used by most RISCs.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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