Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!mailrus!uflorida!gatech!hubcap!dre
From: dre@Sun.COM (David Emberson)
Newsgroups: comp.parallel
Subject: Re: RISC and coherence
Summary: RISC and parallel processing
Keywords: RISC parallel coherence
Message-ID: <3300@hubcap.UUCP>
Date: 19 Oct 88 20:15:32 GMT
Sender: fpst@hubcap.UUCP
Lines: 25
Approved: parallel@hubcap.clemson.edu

[ This is editted due to length.  Hope it is not jibberish.
  --- Steve
]

In article <899@cps3xx.UUCP>, enbody@cpswh.cps.msu.edu (Dr Richard Enbody) writes:
> 
> Question:  ... Two characteristic of RISC processors seem to pose special
> 		  problems for this type of parallel processor ....
> 		  problems (coherence). ... If that data is being
>		  shared with another processor, how is consistency maintained?
> 
> 		  What architectural support exists in current RISC processors?
> 		  What should exist?
> Guesses .....

I don't see why a RISC processor's problems with consistency of register
contents is any different from a CISC processor's.  If you are worried about
the integrity of a data structure, typically you put a semaphore around the
critical section.  I think you are confusing two essentially orthogonal 
issues: synchronization and cache consistency.

Support for cache consistency and synchronization presents essentially the
same set of problems regardless of one's RISC or CISC theology.

			Dave Emberson (dre@sun.com)