Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!bloom-beacon!apple!bionet!agate!ucbvax!hplabs!hp-pcd!hplsla!hpvcla!johne
From: johne@hpvcla.HP.COM (John Eaton)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Re-entrant Operating Systems (was: *nix performance)
Message-ID: <4740026@hpvcla.HP.COM>
Date: 24 Oct 88 16:01:41 GMT
References: <1428@draak.cs.vu.nl>
Organization: Hewlett Packard, Vancouver, WA
Lines: 35

<<<<
< 
< Since NOTHING can interrupt a DMA in progress (including another higher 
< priority DMA request) burst mode DMA transfers, which would be 
< significantly faster than CPU transfers could EVER be, would lock out the 
< channel 0 refresh for too long. Thus DMAs are limited to single byte 
< transfers.  

I have seen some graphics cards that use block mode and burst 8 bytes
out everytime it gets a DACK*. That doesn't violate memory refresh timing.

< Keep in mind that DMA is significantly faster than CPU transfers, even with
< caching, because the DMA chip places the memory address on the bus and then 
< asserts the READ or WRITE line while simultaniously asserting the DMA ACK 
< line. Since the peripheral requesting DMA is well aware of who he/she is 
< and knows that if the memory WRITE line is asserted it must be a peripheral
< READ (and vice versa) the transfer takes place in exactly ONE memory cycle.

The 8237 does a transfer by pulling on IOR* followed one clock later by MW*
or (MR* followed one clock later by IOW*). A peripheral only has to look at 
the DACK line and IO strobes. All IO devices have to decode CPUAEN* so as not
to interfere with a DMA transfer when the memory address equals their IO
address.

The simultanious transfer is not a useful as you might think it would be.
A normal CPU write cycle has data valid at the start of the cycle and DRAM's
can strobe data in at the start of a cycle. IBM's memory control is designed
so that data written into memory must be valid early in the memory cycle 
rather than at the end. So if you are doing a IO->Memory DMA you must wait
almost the entire access time of the peripheral device before starting the
memory write cycle. This really get to be a problem when you try and support
slow PC cards on a fast AT bus.

John Eaton
!hpvcla!johne