Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!lll-tis!lll-winken!scooter!neoucom!wtm
From: wtm@neoucom.UUCP (Bill Mayhew)
Newsgroups: comp.sys.next
Subject: Re: NeXT Memory - No Error Checking or Parity !
Summary: Looks like there isn't any parity checking there
Keywords: Memory,errors,parity
Message-ID: <1382@neoucom.UUCP>
Date: 26 Oct 88 20:35:58 GMT
References: <549@gt-eedsp.UUCP> <3569@phri.UUCP>
Organization: Northeastern Ohio Universities College of Medicine
Lines: 27


I'm looking at the photo of the motherboard for the Next computer
on page 164 of the Nov. 1988 issue of Byte.  The SIMMS would appear
to be 8 * 1 megabit chips.  The accompanying text says that it is
100 nS memory.  There is also a set of four 8K * 8 bit (possibly
HM6164?) cache chips.  The accompanying text says that they are
rated at 45 nS.  There are also four chips identified as "custom
memory buffers" adjacent to the SIMM array.  Last of all, there is
256K of VIDRAM.

For the 32K static RAM, 24K is given to the DSP chip, and 8K goes
to the disk controller.  Apparently the LSI DMA chip must have some
internal smarts.  They do mention that there is a DMA burst mode
that allows 4 long words to be fetched in 9 cycles.

The SCSI controller is a 5390.  The chip is marked NCR in the
photo, but I can't find it in my SMS/OMTI catalog.  I'm willing to
believe the quoted 4 mb/s transfer rate.

I don't know about lack of parity of error correction hardware.
Relative to some of the other goodies included, it doesn't seem
like it would have been that hard to include .. even if it was just
parity.  I'd like to know when my box is making a mistake.  When I
looked inside the Mac II, there didn't seem to be any sort of
parity or error correction there either.  I hope that the kernel
does its own sanity checking in lieu of hardware.

--Bill